C-52 Evaluation Board 62256

A circuit diagram of the C-52 EVB is depicted in Figure 1. See at EA pinfirst, I put EA to Vcc configuring the 89C52 started internal code executionwhen reset. The first 8kB code space, 0000H-1FFFH is then be a monitorprogram, i.e., PAULMON2. A 32kB SRAM 62256 uses 15 lines address, A0-A14,while A15 of the 89C52 connects inverter gate, 74HC00, to CE pin. Thismakes the address space of the SRAM to be 8000H-FFFFH, i.e., A15 must be'1' to enable 62256. See OE pin, RD and PSEN are tied together with ANDgate made by two NAND gates. This makes the address space 8000H-FFFFH seenby 89C52 can be external code and data memory. Thus during in monitor modethat runs under PAULMON2, user may write hex code or download intel HEXfile to 62256. When jump from PAULMON2 to user program and run user program,this space is then be seen by 89C52 as a code space. Since P0 and P2 areused for connecting external RAM, left P1 and P3 for experimenting withreal world interfacing through input/output port. Nowadays there are manyperipheral chips that use serial protocol, say I2C, SPI. Thus only twoport is surely enough.