The pulse signal examined is a driving signal of the power, used in the propulsion power to support, the drive current is usually several mA to several numerous mA, adopt the open-collector gate OC The form is exported, it is usually 12 – 30 V signal. For compatible many kinds of signal levels, and can isolate power type signal and ordinary base band level signal, realize better electromagnetic compatibility, this system adopts the photoelectric coupler as signal isolation and interface device of level switch.
TLP121 is the photoelectric coupler that Toshiba produced, isolates impedance as M grade, its drive current of forward direction IF Maximum 20 mA, rear end switch open and make time ‘s s grade, can respond to the request that the error in emasurement of this system pair is not greater than 1 ms. The input interface resistance is set as the adjustable resistance, can adapt to different input voltages.
The pulse signal interface circuit is shown as in Fig Straight line and loop of pulse signal are connected to the forward end 1, 3 pins of TLP121 in Fig of the photosensitive resister ,Rear end 4, 6 pins of TLP121 in Fig Adopt 5V power in the board to pull upward, sends and deals with FPGA to the interface after having a facelift through the Schmidt circuit 74HC14. When the pulse signal is effective, photosensitive resister forward end have electric current flow through, interface circuit export the intersection of high level and ” the 1 ” ; When pulse signal invalid, interface circuit export the intersection of low level and ” the 0 ” .
interface treatment FPGA
Because need to gauge pulse signals
of No. 80, it is unable to meet concurrent processing’s demands to adopt
the one-chip computer, so choose FPGA and finish the impulse sampling
function. Interface deal with FPGA adopt the intersection of Altera and
FLEX10K50 of Company, working primary frequency is 6 MHz, the storage
chip adopts
EPC1PC8.
Its main function has three parts: Frequency
demultiplication timer, sampled data buffer, peripheral control logic.
FPGA carries on the frequency demultiplication to the main clock, forms
cycle as the clock signal of 1 ms. FPGA every ms finishes running side
by side and gathers the pulse signals of No. 80 once, leaves the data in
the register, send out the interrupt signal to the one-chip computer at
the same time, notify the one-chip computer and initiate the data to
move, and the time counter within the one-chip computer increases by
oneself. The sampled data buffers the module and is used for latching
the pulse signals of No. 80 to the internal register at the same time,
the one-chip computers every ms all read once. Peripheral control logic
is used in the decipher of every control signal of periphery of the
one-chip computer, including control register, every chip control the
signal interpretation, and the realization of other auxiliary functions.
